TSMC and Taiwan’s Industrial Technology Research Institute (ITRI) announced on Thursday that they have jointly developed a Spin-Orbit-Torque Magnetic Random Access Memory (SOT-MRAM) chip, the result of a joint development program announced in 2022. The memory device can be used for in-memory computing architectures and last-level cache boasting non-volatility, low latencies, and power consumption that is 1% of Spin-Transfer-Torque MRAM (STT).
In theory, SOT-MRAM has numerous advantages that make it suitable for caches and in-memory applications. SOT-MRAM can potentially offer higher density than SRAM, which barely accommodates the latest production technologies. Being non-volatile, it also does not consume power when not in use (unlike SRAM), which is beneficial for both data centers and battery-powered applications. SOT-MRAM is theoretically capable of latencies of up to 10ns, which is certainly slower compared to SRAM (SRAM’s read and write latency are typically in the range of 1-2ns), but is slightly faster than DRAM (DDR5 has latencies around 14ms) and considerably faster than 3D TLC NAND (which has read latencies between 50 and 100 microseconds).
“This single cell simultaneously achieves low energy consumption and high-speed operation, achieving speeds of up to 10 ns,” said Dr. Shih-Chieh Chang, Director General of ITRI’s Electronics and Optoelectronics Systems Research Labs. “Its overall computing performance can be further enhanced when integrated into memory circuit design. Looking ahead, this technology has potential applications in high-performance computing (HPC), artificial intelligence (AI), automotive chips, and much more.”
Spin-Orbit-Torque Magnetic Random Access Memory (SOT-MRAM) and Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) are types of non-volatile memory technology that uses magnetic states to store data. In both SOT and STT MRAM, the memory cell relies on a structure called a magnetic tunnel junction (MTJ) that comprises a thin free and fixed magnetic layer (e.g., CoFeB) stacked vertically with a very thin dielectric layer (e.g., MgO) sandwiched between them, and an additional layer of ‘heavy metal’ (e.g., tungsten) adjacent to one of the magnetic layers.
Data is written to the memory cell by changing the magnetization in the free layer (which acts as the ‘storage’ layer in the MRAM bit cell) by passing a current through the heavy metal layer, which generates a spin current and injects it into the adjacent magnetic layer, changing its orientation and thus altering its state. Data reading involves assessing the magnetoresistance of the MTJ by directing a current through the junction. The main difference between STT and SOT-MRAM resides in the current injection geometry used for the writing process and, apparently, the SOT method ensures lower power consumption and device longevity.
Although SOT-MRAM offers lower standby power than SRAM, it requires high currents for writing operations, so its dynamic power consumption is still quite high. Additionally, SOT-SRAM cells are still larger than SRAM cells and are more challenging to fabricate. As a result, while SOT-SRAM technology seems promising, it is unlikely to replace SRAM anytime soon. However, for in-memory computing applications, SOT-MRAM may make a lot of sense, if not now, then when TSMC learns how to make SOT-MRAM economically.